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* sf2: add NOTES about using yosys for smartfusion2 and igloo2Tristan Gingold2022-08-311-0/+84
* sf2: add a test for $alu gateTristan Gingold2022-08-311-0/+22
* sf2: suport $alu gate and ARI1 implementationTristan Gingold2022-08-312-2/+65
* synth_sf2: purge on last cleanTristan Gingold2022-08-311-2/+2
* sf2/cells_sim.v: add XTLOSC, SYSRESET cellsTristan Gingold2022-08-311-1/+110
* sf2/cells_sim.v: add IOSTD parameter to I/O cellsTristan Gingold2022-08-311-0/+11
* synth_sf2: add -discard-ffinit option to discard ff initial valueTristan Gingold2022-08-311-1/+11
* Fitting help messages to 80 character widthKrystalDelusion2022-08-246-20/+25
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
* Order ports with default assignments firstSean Anderson2022-08-091-10/+38
* nexus: Fix BRAM mapping.Marcelina Kościelnicka2022-08-091-18/+56
* Merge pull request #3397 from pepijndevos/patch-2Miodrag Milanović2022-07-061-1/+0
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| * Apicula now supports lutramPepijn de Vos2022-07-031-1/+0
* | Fix static initialization, fixes mingw buildMiodrag Milanovic2022-07-041-20/+21
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* gatemate: Add LUT tree library scriptgatecat2022-06-276-6/+591
* gatemate: Add preliminary sim models for LUT tree structuresgatecat2022-06-271-0/+44
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-024-7/+64
* gatemate: Fix minor issues with `memory_libmap` (#3343)Patrick Urban2022-05-272-28/+39
* gatemate: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-781/+927
* machxo2: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-187-1/+578
* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-90/+163
* anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-303/+585
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-188-458/+293
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1837-2269/+4525
* gowin: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-266/+576
* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1810-517/+677
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-466/+584
* Add missing parameters for ecp5Rick Luiken2022-04-252-1/+2
* gowin: Add oscillator primitivesTim Pambor2022-03-281-0/+34
* xilinx: Add RAMB4* blackboxesMarcelina Kościelnicka2022-03-212-1/+695
* gowin: add support for Double Data Rate primitivesYRabbit2022-03-141-0/+25
* intel_alm: M10K write-enable is negative-trueLofty2022-03-096-7/+28
* gowin: Remove unnecessary attributesYRabbit2022-02-241-5/+0
* gowin: Add support for true differential outputYRabbit2022-02-241-0/+11
* ecp5: Do not use specify in generate in cells_sim.v.Marcelina Kościelnicka2022-02-211-28/+15
* gowin: Add remaining block RAM blackboxes.Marcelina Kościelnicka2022-02-121-72/+527
* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-092-41/+241
* ecp5: Fix DPR16X4 sim model.Marcelina Kościelnicka2022-02-091-1/+1
* nexus: Fix arith_map CO signal.Marcelina Kościelnicka2022-02-061-1/+1
* Fix the help message of synth_quicklogic.Xing GUO2022-01-311-2/+2
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-282-24/+87
* nexus: Fix BB sim modelgatecat2022-01-191-2/+2
* Removed dbits 8 since 9 will always be pickedMiodrag Milanovic2022-01-191-2/+0
* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-196-1/+269
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| * anlogic: support BRAM mappingIcenowy Zheng2021-12-176-1/+269
* | intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
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* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
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