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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-03-15 07:41:30 +1000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-03-14 23:14:21 +0100 |
| commit | 19b7633aca6335bfdf79ab1fd71f99060f6e04ca (patch) | |
| tree | bb6734e55632eea8d2a174c185126df4d05c6acc /techlibs | |
| parent | 25d6fdfea7b40de852e00df405f018723b98b6f1 (diff) | |
| download | yosys-19b7633aca6335bfdf79ab1fd71f99060f6e04ca.tar.gz yosys-19b7633aca6335bfdf79ab1fd71f99060f6e04ca.tar.bz2 yosys-19b7633aca6335bfdf79ab1fd71f99060f6e04ca.zip | |
gowin: add support for Double Data Rate primitives
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index b07ee6924..64b76139c 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -590,6 +590,31 @@ module TLVDS_OBUF (I, O, OB); assign OB = ~I; endmodule +(* blackbox *) +module ODDR(D0, D1, TX, CLK, Q0, Q1); + input D0; + input D1; + input TX; + input CLK; + output Q0; + output Q1; + parameter TXCLK_POL = 0; + parameter INIT = 0; +endmodule + +(* blackbox *) +module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1); + input D0; + input D1; + input CLEAR; + input TX; + input CLK; + output Q0; + output Q1; + parameter TXCLK_POL = 0; + parameter INIT = 0; +endmodule + module GSR (input GSRI); wire GSRO = GSRI; endmodule |