sf2: add NOTES about using yosys for smartfusion2 and igloo2

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diff --git a/techlibs/sf2/NOTES.txt b/techlibs/sf2/NOTES.txt
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+Using yosys with Libero Soc
+===========================
+
+Yosys does synthesis and therefore could be used instead of Synplify in
+the Libero workflow.  You still have to use LiberoSoc for place, route,
+bitsteam generation, timing analysis...
+
+This is unfortunately not trivial, but this is also not too difficult.
+When you run the Synthesize step, three tools are executed one after the other.
+
+You'd better to write a simple script, like this one (assuming the top module
+is top):
+
+----------- run_yosys.sh --------------
+#!/bin/sh
+
+set -e
+
+yosys -p 'read_verilog hdl/top.v; synth_sf2; write_verilog -defparam synthesis/top_yosys.v'
+
+rwnetlist64 --script yosys/rwnetlist.tcl
+
+echo "##### run g4compile"
+
+g4compile --script yosys/run_compile.tcl
+
+libero SCRIPT:run_yosys.tcl
+------------------------------------
+
+Yosys will do the synthesis and write a netlist in verilog.  Then you have
+to call microsemi tools to build the netlist for the P&R tools.
+
+The first one do a file format conversion.  During the normal workflow, the
+tcl file is created in a temporary file.  You can use this one:
+
+------------- tcl/rwnetlist.tcl ---------
+set_device -fam SmartFusion2
+read_verilog  \
+    -file {../synthesis/top_yosys.v}
+write_adl -file {../designer/top/top.adl}
+----------------------------------------
+
+Probably, you will have to change the family for Igloo2.
+
+The second command link the netlists.  The tcl script is generated by
+liberoSoc in designer/top/run_compile.tcl.  You can use it as it.
+The "Source Files" value could be changed but it looks to have no effect.
+This commands create the .afl file.
+
+Then you can use the normal flow.  This is done by the run_yosys.tcl:
+
+-----------  run_yosys.tcl --------------
+open_project -file {./top.prjx}
+run_tool -name {PLACEROUTE} 
+run_tool -name {PROGRAMDEVICE} 
+-----------------------------------------
+
+
+Using MSS, HPMS or other IPs
+============================
+
+This works.  You'd better to configure CCC (~ the PLL) and the MSS using
+liberoSoc as the configuration bits are not documented.
+Then you have to manually gather the HDL sources generated for the IPs.
+They are in the component subdirectory. Sometimes there are both a _syn and
+a _pre version of the same file.  They are for symplify and precision.
+Use only once, the symplify version should be OK.  For the MSS, these are the
+blackboxes, so you don't need them.
+
+SYSRESET and XTLOSC have one fake port.  This is handled, provided you use
+the blackbox module declared by Yosys in cell_sim.v.  This is OK by default
+too.
+
+
+What is missing
+===============
+
+Always flatten your design (this is the default).  Hierarchical designs
+don't work.
+
+Constraints (SDC files) are not supported by Yosys.  Furthermore, due to
+flattening and optimization, nets name may change.
+
+More testing...