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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-06 12:48:44 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-06 13:05:30 +0100 |
| commit | 958c3a46ad84917e6f1ba06f5eac3ccda1964c2b (patch) | |
| tree | 79dac7f54489c79849a3a0bff1c0e0d337a99427 /techlibs | |
| parent | 675a7bd22c38451e5965b02100edeabb342971bf (diff) | |
| download | yosys-958c3a46ad84917e6f1ba06f5eac3ccda1964c2b.tar.gz yosys-958c3a46ad84917e6f1ba06f5eac3ccda1964c2b.tar.bz2 yosys-958c3a46ad84917e6f1ba06f5eac3ccda1964c2b.zip | |
nexus: Fix arith_map CO signal.
Fixes #3187.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/nexus/arith_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/nexus/arith_map.v b/techlibs/nexus/arith_map.v index 9a1fedfc8..81ab7ba54 100644 --- a/techlibs/nexus/arith_map.v +++ b/techlibs/nexus/arith_map.v @@ -90,7 +90,7 @@ module _80_nexus_alu (A, B, CI, BI, X, Y, CO); assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); if (i+1 < Y_WIDTH) begin - assign CO[i + 1] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); + assign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1])); assign Y[i+1] = Y1[i]; end end endgenerate |