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| author | Xing GUO <higuoxing@gmail.com> | 2022-01-30 22:10:05 +0800 |
|---|---|---|
| committer | Xing GUO <higuoxing@gmail.com> | 2022-01-31 02:23:59 +0800 |
| commit | 0520e999680c1e371391fcb6335150cbc5f97b66 (patch) | |
| tree | 9c53aae8842633bbf077451827e5cf02f9883f54 /techlibs | |
| parent | 07a657fb0ca08012af3de410520458af255b1097 (diff) | |
| download | yosys-0520e999680c1e371391fcb6335150cbc5f97b66.tar.gz yosys-0520e999680c1e371391fcb6335150cbc5f97b66.tar.bz2 yosys-0520e999680c1e371391fcb6335150cbc5f97b66.zip | |
Fix the help message of synth_quicklogic.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/quicklogic/synth_quicklogic.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index a67b167b8..754de2de6 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -225,8 +225,8 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("verilog")) { - if (!verilog_file.empty()) { - run("write_verilog -noattr -nohex " + verilog_file); + if (!verilog_file.empty() || help_mode) { + run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str())); } } } |