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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 05:35:05 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 09:02:13 +0100 |
| commit | ac2bb70b5287af66c7bc6b7ed532575c1955c75e (patch) | |
| tree | e4e811aa7f4dc849967a341c22cd26adb518f73e /techlibs | |
| parent | 23d062fea3416ea077f41ea2b71c11b14ea2fe87 (diff) | |
| download | yosys-ac2bb70b5287af66c7bc6b7ed532575c1955c75e.tar.gz yosys-ac2bb70b5287af66c7bc6b7ed532575c1955c75e.tar.bz2 yosys-ac2bb70b5287af66c7bc6b7ed532575c1955c75e.zip | |
ecp5: Fix DPR16X4 sim model.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 357fd9173..a5f905cf8 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -204,7 +204,7 @@ module TRELLIS_DPR16X4 ( integer i; initial begin for (i = 0; i < 16; i = i + 1) - mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]}; + mem[i] <= INITVAL[4*i +: 4]; end wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; |