iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	1	-590/+0
*	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	1	-0/+20
*	xilinx: Add simulation models for IOBUF and OBUFT.	Marcin Kościelnicki	2019-11-26	1	-23/+0
*	xilinx: Add simulation models for MULT18X18* and DSP48A*.	Marcin Kościelnicki	2019-11-19	1	-127/+0
*	synth_xilinx: Merge blackbox primitive libraries.	Marcin Kościelnicki	2019-11-06	1	-0/+29339
*	xilinx: Make blackbox library family-dependent.	Marcin Kościelnicki	2019-09-15	1	-4099/+0
*	move attributes to wires	Marcin Kościelnicki	2019-08-13	1	-91/+230
*	Add clock buffer insertion pass, improve iopadmap.	Marcin Kościelnicki	2019-08-13	1	-2/+88
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-25	1	-7/+0
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\| *	Add RAM32X1D support	Eddie Hung	2019-06-24	1	-18/+0
* \|	Add whitebox support to DRAM	Eddie Hung	2019-05-23	1	-18/+0
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*	Merge remote-tracking branch 'origin' into xc7srl	Eddie Hung	2019-04-20	1	-38/+0
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\| *	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	1	-38/+0
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-22	1	-19/+24
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\| *	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	1	-19/+24
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-0/+19
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\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-0/+19
* \|	Remove SRL16/32 from cells_xtra	Eddie Hung	2019-02-28	1	-16/+0
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*	Add support for Xilinx PS7 block	Eddie Hung	2018-11-10	1	-0/+623
*	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-04	1	-0/+12
*	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-03	1	-0/+1
*	Added black box modules for all the 7-series design elements (as listed in ug...	Clifford Wolf	2016-03-19	1	-0/+3293