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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:16:50 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:16:50 -0700 |
commit | efd04880dbeb2021c503c82ad962fe8c5d6802d4 (patch) | |
tree | 0d2f1d1c8c211d24b2d3f1878b7c70f4bd98997f /techlibs/xilinx/cells_xtra.v | |
parent | fb8fab4a29e5a3978cadf2b1bd8920b772150028 (diff) | |
download | yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.tar.gz yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.tar.bz2 yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.zip |
Add RAM32X1D support
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index fbcc74682..6220da703 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3655,17 +3655,6 @@ module PULLUP (...); output O; endmodule -module RAM128X1D (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input [6:0] A; - input [6:0] DPRA; - input D; - input WCLK; - input WE; -endmodule - module RAM128X1S (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3705,13 +3694,6 @@ module RAM32M (...); input WE; endmodule -module RAM32X1D (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; -endmodule - module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; |