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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 11:21:07 -0800 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 12:02:27 -0800 |
| commit | 3090951d54859c331d28232481361bb9c26b3d48 (patch) | |
| tree | 24973f1f4bea3abbca07c82729086423a101f495 /techlibs/xilinx/cells_xtra.v | |
| parent | 66fd6396d4795ea9559cbbd1560387e7d7e79596 (diff) | |
| download | yosys-3090951d54859c331d28232481361bb9c26b3d48.tar.gz yosys-3090951d54859c331d28232481361bb9c26b3d48.tar.bz2 yosys-3090951d54859c331d28232481361bb9c26b3d48.zip | |
Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8d8b91ddc..995d62e18 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3695,6 +3695,25 @@ module RAM128X1S (...); input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; endmodule +module RAM128X1D ( + output DPO, SPO, + input D, WCLK, WE, + input [6:0] A, DPRA +); + parameter [127:0] INIT = 128'bx; + parameter IS_WCLK_INVERTED = 0; +endmodule + +module RAM64X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter [63:0] INIT = 64'bx; + parameter IS_WCLK_INVERTED = 0; +endmodule + module RAM256X1S (...); parameter [255:0] INIT = 256'h0; parameter [0:0] IS_WCLK_INVERTED = 1'b0; |