iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Improve flip-flop handling.	Marcin Kościelnicki	2019-12-18	4	-38/+228
*	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	Eddie Hung	2019-12-16	3	-12/+301
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\| *	Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...	Eddie Hung	2019-12-16	1	-2/+8
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\| \| *	Populate DID/DOD even if unused	Eddie Hung	2019-12-16	1	-2/+8
\| * \|	Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q	Eddie Hung	2019-12-16	2	-6/+6
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\| *	Disable RAM16X1D match rule; carry-over from LUT4 arches	Eddie Hung	2019-12-13	1	-6/+9
\| *	RAM64M8 to also have [5:0] for address	Eddie Hung	2019-12-13	1	-8/+8
\| *	Add RAM32X6SDP and RAM64X3SDP modes	Eddie Hung	2019-12-12	2	-8/+120
\| *	Fix RAM64M model to have 6 bit address bus	Eddie Hung	2019-12-12	1	-4/+4
\| *	Add memory rules for RAM16X1D, RAM32M, RAM64M	Eddie Hung	2019-12-12	2	-0/+168
* \|	Add unconditional match blocks for force RAM	Eddie Hung	2019-12-16	1	-4/+36
* \|	Update xc7/xcu bram rules	Eddie Hung	2019-12-16	1	-8/+4
* \|	Removing fixed attribute value to !ramstyle rules	Diego H	2019-12-15	1	-4/+4
* \|	Merging attribute rules into a single match block; Adding tests	Diego H	2019-12-15	1	-18/+12
* \|	Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific	Diego H	2019-12-13	1	-0/+19
* \|	Merge pull request #1533 from dh73/bram_xilinx	Eddie Hung	2019-12-13	1	-6/+9
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\| *	Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.	Diego H	2019-12-12	1	-5/+5
\| *	Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1	Diego H	2019-12-12	1	-2/+2
\| *	Merge https://github.com/YosysHQ/yosys into bram_xilinx	Diego H	2019-12-12	5	-633/+868
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\| * \|	Adjusting Vivado's BRAM min bits threshold for RAMB18E1	Diego H	2019-11-27	1	-2/+5
* \| \|	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
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* \|	xilinx: Add tristate buffer mapping. (#1528)	Marcin Kościelnicki	2019-12-04	2	-9/+16
* \|	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	3	-624/+831
* \|	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	2	-0/+21
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*	xilinx: Add simulation models for IOBUF and OBUFT.	Marcin Kościelnicki	2019-11-26	3	-25/+30
*	clkbufmap: Add support for inverters in clock path.	Marcin Kościelnicki	2019-11-25	1	-1/+5
*	xilinx: Use INV instead of LUT1 when applicable	Marcin Kościelnicki	2019-11-25	1	-2/+6
*	xilinx: Add simulation models for MULT18X18* and DSP48A*.	Marcin Kościelnicki	2019-11-19	3	-132/+516
*	synth_xilinx: Merge blackbox primitive libraries.	Marcin Kościelnicki	2019-11-06	11	-23234/+29820
*	xilinx: Add URAM288 mapping for xcup	David Shah	2019-10-23	5	-2/+92
*	xilinx: Add support for UltraScale[+] BRAM mapping	David Shah	2019-10-23	7	-416/+1062
*	xilinx: Support multiplier mapping for all families.	Marcin Kościelnicki	2019-10-22	9	-9/+269
*	Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg	Clifford Wolf	2019-10-22	1	-0/+1
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\| *	Call memory_dff before DSP mapping to reserve registers (fixes #1447)	N. Engelhardt	2019-10-17	1	-0/+1
* \|	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	1	-1/+1
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*	xilinx: Add simulation model for IBUFG.	Marcin Kościelnicki	2019-10-10	5	-33/+14
*	Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9	Eddie Hung	2019-10-08	11	-112/+121
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\| *	Merge branch 'master' into eddie/abc_to_abc9	Eddie Hung	2019-10-04	4	-181/+9
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\| * \|	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	11	-111/+120
* \| \|	Add comment on why partial multipliers are 18x18	Eddie Hung	2019-10-04	1	-4/+8
* \| \|	Fix typo in check_label()	Eddie Hung	2019-10-04	1	-1/+1
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* \|	Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`	Eddie Hung	2019-10-04	1	-2/+6
* \|	Remove DSP48E1 from *_cells_xtra.v	Eddie Hung	2019-10-04	3	-178/+2
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*	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	Eddie Hung	2019-09-30	6	-122/+46
*	synth_xilinx: Support latches, remove used-up FF init values.	Marcin Kościelnicki	2019-09-30	2	-2/+76
*	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	11	-21/+3000
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\| *	Re-order	Eddie Hung	2019-09-27	1	-1/+1
\| *	Typo	Eddie Hung	2019-09-26	1	-1/+1
\| *	select once	Eddie Hung	2019-09-26	1	-3/+5
\| *	Stop trying to be too smart by prematurely optimising	Eddie Hung	2019-09-26	1	-1/+3