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authorEddie Hung <eddieh@ece.ubc.ca>2019-02-28 13:56:45 -0800
committerEddie Hung <eddieh@ece.ubc.ca>2019-02-28 13:56:45 -0800
commit1da090966263318c46dd1d91d2f1f4d11238c2c1 (patch)
tree2642889e995a7ebbc0a447e1b7e1b40371edbdf1 /techlibs/xilinx/cells_xtra.v
parent73ddab6960a02aef0c5f9ccee8cee2e666778c06 (diff)
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Remove SRL16/32 from cells_xtra
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
-rw-r--r--techlibs/xilinx/cells_xtra.v16
1 files changed, 0 insertions, 16 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 8d8b91ddc..21db6a6bd 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3824,22 +3824,6 @@ module ROM64X1 (...);
input A0, A1, A2, A3, A4, A5;
endmodule
-module SRL16E (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- output Q;
- input A0, A1, A2, A3, CE, CLK, D;
-endmodule
-
-module SRLC32E (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- output Q;
- output Q31;
- input [4:0] A;
- input CE, CLK, D;
-endmodule
-
module STARTUPE2 (...);
parameter PROG_USR = "FALSE";
parameter real SIM_CCLK_FREQ = 0.0;