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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 10:41:43 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 10:41:43 -0700 |
commit | 13ad19482f2b81a21d0e374a030cb466ed7afb55 (patch) | |
tree | 87050e358eb62f0363c1f4028fea4038a3fa52e7 /techlibs/xilinx/cells_xtra.v | |
parent | 6797f6b6c4660622dbde27ced83fdd37a874f00d (diff) | |
parent | e3687f6f4e10789223213949b8490bd83ec285f2 (diff) | |
download | yosys-13ad19482f2b81a21d0e374a030cb466ed7afb55.tar.gz yosys-13ad19482f2b81a21d0e374a030cb466ed7afb55.tar.bz2 yosys-13ad19482f2b81a21d0e374a030cb466ed7afb55.zip |
Merge remote-tracking branch 'origin' into xc7srl
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 06c868080..fbcc74682 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -30,29 +30,6 @@ module BUFGCE_1 (...); input CE, I; endmodule -module BUFGCTRL (...); - output O; - input CE0; - input CE1; - input I0; - input I1; - input IGNORE0; - input IGNORE1; - input S0; - input S1; - parameter integer INIT_OUT = 0; - parameter PRESELECT_I0 = "FALSE"; - parameter PRESELECT_I1 = "FALSE"; - parameter [0:0] IS_CE0_INVERTED = 1'b0; - parameter [0:0] IS_CE1_INVERTED = 1'b0; - parameter [0:0] IS_I0_INVERTED = 1'b0; - parameter [0:0] IS_I1_INVERTED = 1'b0; - parameter [0:0] IS_IGNORE0_INVERTED = 1'b0; - parameter [0:0] IS_IGNORE1_INVERTED = 1'b0; - parameter [0:0] IS_S0_INVERTED = 1'b0; - parameter [0:0] IS_S1_INVERTED = 1'b0; -endmodule - module BUFGMUX (...); parameter CLK_SEL_TYPE = "SYNC"; output O; @@ -77,15 +54,6 @@ module BUFH (...); input I; endmodule -module BUFHCE (...); - parameter CE_TYPE = "SYNC"; - parameter integer INIT_OUT = 0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - output O; - input CE; - input I; -endmodule - module BUFIO (...); output O; input I; @@ -2420,12 +2388,6 @@ module LDPE (...); input D, G, GE, PRE; endmodule -module LUT6_2 (...); - parameter [63:0] INIT = 64'h0000000000000000; - input I0, I1, I2, I3, I4, I5; - output O5, O6; -endmodule - module MMCME2_ADV (...); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; |