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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
| commit | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (patch) | |
| tree | 04dc0222fd51dd70edef52b733cecd2a9179c093 /techlibs/xilinx/cells_xtra.v | |
| parent | d2fed0a7f1bb72ee285657b974f4996c77641a23 (diff) | |
| parent | ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (diff) | |
| download | yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.gz yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.bz2 yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 0ec3d0df0..15fa1b63a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3694,13 +3694,6 @@ module RAM32M (...); input WE; endmodule -module RAM32X1D (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; -endmodule - module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; |