diff options
author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-12 09:30:49 -0700 |
---|---|---|
committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-12 09:35:15 -0700 |
commit | 1f9235ede5d5fee4ce0ad13c2905f624e9493426 (patch) | |
tree | 447fb949a085354261f5babdf30173e4aff24e30 /techlibs/xilinx/cells_xtra.v | |
parent | e107ccdde82247e28c9c994240e4d4bf694f673f (diff) | |
download | yosys-1f9235ede5d5fee4ce0ad13c2905f624e9493426.tar.gz yosys-1f9235ede5d5fee4ce0ad13c2905f624e9493426.tar.bz2 yosys-1f9235ede5d5fee4ce0ad13c2905f624e9493426.zip |
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 497518d35..4fb6798be 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -30,29 +30,6 @@ module BUFGCE_1 (...); input CE, I; endmodule -module BUFGCTRL (...); - output O; - input CE0; - input CE1; - input I0; - input I1; - input IGNORE0; - input IGNORE1; - input S0; - input S1; - parameter integer INIT_OUT = 0; - parameter PRESELECT_I0 = "FALSE"; - parameter PRESELECT_I1 = "FALSE"; - parameter [0:0] IS_CE0_INVERTED = 1'b0; - parameter [0:0] IS_CE1_INVERTED = 1'b0; - parameter [0:0] IS_I0_INVERTED = 1'b0; - parameter [0:0] IS_I1_INVERTED = 1'b0; - parameter [0:0] IS_IGNORE0_INVERTED = 1'b0; - parameter [0:0] IS_IGNORE1_INVERTED = 1'b0; - parameter [0:0] IS_S0_INVERTED = 1'b0; - parameter [0:0] IS_S1_INVERTED = 1'b0; -endmodule - module BUFGMUX (...); parameter CLK_SEL_TYPE = "SYNC"; output O; @@ -77,15 +54,6 @@ module BUFH (...); input I; endmodule -module BUFHCE (...); - parameter CE_TYPE = "SYNC"; - parameter integer INIT_OUT = 0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - output O; - input CE; - input I; -endmodule - module BUFIO (...); output O; input I; @@ -2420,12 +2388,6 @@ module LDPE (...); input D, G, GE, PRE; endmodule -module LUT6_2 (...); - parameter [63:0] INIT = 64'h0000000000000000; - input I0, I1, I2, I3, I4, I5; - output O5, O6; -endmodule - module MMCME2_ADV (...); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; |