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* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-201-0/+1
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* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-378/+0
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* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-271-0/+1
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* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-051-0/+16
|\ | | | | abc9: add support for required times
| * Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-271-0/+16
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* | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-291-43/+0
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* xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-191-139/+0
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* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-21/+0
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* xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-041-590/+0
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* xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-291-0/+20
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* xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-261-23/+0
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* xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-191-127/+0
| | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-061-0/+29339
| | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
* xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-4099/+0
| | | | Fixes #1246.
* move attributes to wiresMarcin Kościelnicki2019-08-131-91/+230
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* Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-2/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-251-7/+0
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| * Add RAM32X1D supportEddie Hung2019-06-241-18/+0
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* | Add whitebox support to DRAMEddie Hung2019-05-231-18/+0
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* Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-201-38/+0
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| * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-121-38/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-221-19/+24
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-221-19/+24
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-0/+19
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| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-0/+19
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove SRL16/32 from cells_xtraEddie Hung2019-02-281-16/+0
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* Add support for Xilinx PS7 blockEddie Hung2018-11-101-0/+623
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* Add inout ports to cells_xtra.vClifford Wolf2018-10-041-0/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Added black box modules for all the 7-series design elements (as listed in ↵Clifford Wolf2016-03-191-0/+3293
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