xilinx: Add simulation models for remaining CLB primitives.

1 files changed, 0 insertions, 139 deletions

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 66b7c583f..c3e5c72f9 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,144 +1,5 @@
 // Created by cells_xtra.py from Xilinx models
 
-module FDCPE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_C_INVERTED = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    output Q;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_C_INVERTED" *)
-    input C;
-    input CE;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
-module LDCPE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_D_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_GE_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    (* invertible_pin = "IS_D_INVERTED" *)
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    (* invertible_pin = "IS_GE_INVERTED" *)
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
-module AND2B1L (...);
-    parameter [0:0] IS_SRI_INVERTED = 1'b0;
-    output O;
-    input DI;
-    (* invertible_pin = "IS_SRI_INVERTED" *)
-    input SRI;
-endmodule
-
-module OR2L (...);
-    parameter [0:0] IS_SRI_INVERTED = 1'b0;
-    output O;
-    input DI;
-    (* invertible_pin = "IS_SRI_INVERTED" *)
-    input SRI;
-endmodule
-
-module MUXF5 (...);
-    output O;
-    input I0;
-    input I1;
-    input S;
-endmodule
-
-module MUXF6 (...);
-    output O;
-    input I0;
-    input I1;
-    input S;
-endmodule
-
-module MUXF9 (...);
-    output O;
-    input I0;
-    input I1;
-    input S;
-endmodule
-
-module CARRY8 (...);
-    parameter CARRY_TYPE = "SINGLE_CY8";
-    output [7:0] CO;
-    output [7:0] O;
-    input CI;
-    input CI_TOP;
-    input [7:0] DI;
-    input [7:0] S;
-endmodule
-
-module ORCY (...);
-    output O;
-    input CI;
-    input I;
-endmodule
-
-module MULT_AND (...);
-    output LO;
-    input I0;
-    input I1;
-endmodule
-
-module SRL16 (...);
-    parameter [15:0] INIT = 16'h0000;
-    output Q;
-    input A0;
-    input A1;
-    input A2;
-    input A3;
-    (* clkbuf_sink *)
-    input CLK;
-    input D;
-endmodule
-
-module SRLC16 (...);
-    parameter [15:0] INIT = 16'h0000;
-    output Q;
-    output Q15;
-    input A0;
-    input A1;
-    input A2;
-    input A3;
-    (* clkbuf_sink *)
-    input CLK;
-    input D;
-endmodule
-
-module CFGLUT5 (...);
-    parameter [31:0] INIT = 32'h00000000;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    output CDO;
-    output O5;
-    output O6;
-    input I4;
-    input I3;
-    input I2;
-    input I1;
-    input I0;
-    input CDI;
-    input CE;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLK_INVERTED" *)
-    input CLK;
-endmodule
-
 module RAMB16_S1 (...);
     parameter [0:0] INIT = 1'h0;
     parameter [0:0] SRVAL = 1'h0;