diff options
author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 18:59:40 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-02-05 18:59:40 +0100 |
commit | 0671ae7d79ead3f7c109ed41ea7ad5e5767f418a (patch) | |
tree | eff88fad0d90d4a6fd92c6ebda512d5bc010dc2b /techlibs/xilinx/cells_xtra.v | |
parent | 34d2fbd2f96a8789aa7eb655318308e11949eb7a (diff) | |
parent | 21ce1b37fbc93562942c10f631c7f415f8fdba2e (diff) | |
download | yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.gz yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.bz2 yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.zip |
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 54e48f1a6..e87f4ec76 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -4518,13 +4518,21 @@ module RAMB18E1 (...); input RSTREGARSTREG; (* invertible_pin = "IS_RSTREGB_INVERTED" *) input RSTREGB; + (* abc9_required=566 *) input [13:0] ADDRARDADDR; + (* abc9_required=566 *) input [13:0] ADDRBWRADDR; + (* abc9_required=737 *) input [15:0] DIADI; + (* abc9_required=737 *) input [15:0] DIBDI; + (* abc9_required=737 *) input [1:0] DIPADIP; + (* abc9_required=737 *) input [1:0] DIPBDIP; + (* abc9_required=532 *) input [1:0] WEA; + (* abc9_required=532 *) input [3:0] WEBWE; endmodule @@ -4742,13 +4750,21 @@ module RAMB36E1 (...); input REGCEB; input INJECTDBITERR; input INJECTSBITERR; + (* abc9_required=566 *) input [15:0] ADDRARDADDR; + (* abc9_required=566 *) input [15:0] ADDRBWRADDR; + (* abc9_required=737 *) input [31:0] DIADI; + (* abc9_required=737 *) input [31:0] DIBDI; + (* abc9_required=737 *) input [3:0] DIPADIP; + (* abc9_required=737 *) input [3:0] DIPBDIP; + (* abc9_required=532 *) input [3:0] WEA; + (* abc9_required=532 *) input [7:0] WEBWE; endmodule |