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* xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-191-139/+0
* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-21/+0
* xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-041-590/+0
* xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-291-0/+20
* xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-261-23/+0
* xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-191-127/+0
* synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-061-0/+29339
* xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-4099/+0
* move attributes to wiresMarcin Kościelnicki2019-08-131-91/+230
* Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-2/+88
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-251-7/+0
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| * Add RAM32X1D supportEddie Hung2019-06-241-18/+0
* | Add whitebox support to DRAMEddie Hung2019-05-231-18/+0
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* Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-201-38/+0
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| * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-121-38/+0
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-221-19/+24
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-221-19/+24
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-0/+19
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| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-0/+19
* | Remove SRL16/32 from cells_xtraEddie Hung2019-02-281-16/+0
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* Add support for Xilinx PS7 blockEddie Hung2018-11-101-0/+623
* Add inout ports to cells_xtra.vClifford Wolf2018-10-041-0/+12
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-191-0/+3293