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path: root/techlibs/xilinx/cells_map.v
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-0/+6
* xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-181-0/+27
* xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-041-0/+8
* Use abc_{map,unmap,model}.vEddie Hung2019-08-201-2/+0
* xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
* Add some spacingEddie Hung2019-07-101-9/+9
* Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
* Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
* Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
* Fix typo and commentsEddie Hung2019-07-091-4/+4
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-091-19/+25
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| * Cleanup SRL inference/make more consistentEddie Hung2019-06-291-19/+25
* | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
* | Add one more commentEddie Hung2019-07-081-0/+3
* | Less thinkingEddie Hung2019-07-081-3/+3
* | RewordEddie Hung2019-07-081-2/+2
* | Map $__XILINX_SHIFTX in a more balanced mannerEddie Hung2019-07-081-36/+49
* | Fixes for 2:1 muxesEddie Hung2019-07-081-4/+29
* | Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-011-29/+29
* | Fix broken MUXFx box, use MUXF7x2 box insteadEddie Hung2019-07-011-29/+29
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-291-16/+6
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* | Restore $__XILINX_MUXF78 const optimisationEddie Hung2019-06-281-24/+24
* | Clean up trimming leading 1'bx in A during techmappnigEddie Hung2019-06-281-15/+9
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-281-4/+2
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| * Reduce diff with upstreamEddie Hung2019-06-271-4/+2
* | This optimisation doesn't seem to work...Eddie Hung2019-06-251-24/+24
* | Reduce MuxFx resources in mux techmappingEddie Hung2019-06-241-10/+30
* | Reduce number of decomposed muxes during techmapEddie Hung2019-06-241-14/+11
* | Revert "Fix techmapping muxes some more"Eddie Hung2019-06-241-4/+4
* | Fix techmapping muxes some moreEddie Hung2019-06-241-4/+4
* | Fix mux techmappingEddie Hung2019-06-241-19/+20
* | Change synth_xilinx's -nomux to -minmuxf <int>Eddie Hung2019-06-241-25/+41
* | Fix spacingEddie Hung2019-06-211-3/+3
* | Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-211-4/+12
* | Revert "Remove wide mux inference"Eddie Hung2019-06-141-0/+120
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* Fix name clashEddie Hung2019-06-131-4/+8
* Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
* Remove wide mux inferenceEddie Hung2019-06-121-120/+0
* $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-061-9/+9
* Fix muxcover and its techmappingEddie Hung2019-06-061-2/+2
* Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-061-0/+12
* CleanupEddie Hung2019-06-051-10/+0
* Fix name clashEddie Hung2019-06-041-11/+11
* Add mux_map.v for wide muxEddie Hung2019-06-041-21/+14
* Fix/workaround symptom unveiled by #1023Eddie Hung2019-05-211-4/+14
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-211-6/+8
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| * Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
* | Trim off leading 1'bx in AEddie Hung2019-05-021-7/+20
* | Add don't care optimisationEddie Hung2019-05-021-0/+11
* | Revert to pre-muxcover approachEddie Hung2019-05-021-17/+77
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