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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 14:15:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 14:15:31 -0700 |
| commit | 2e7992efffa1d75cf69c8942d03b53e1b6ec2895 (patch) | |
| tree | 0f044972e45904485540d72060f435e7f9d27e9a /techlibs/xilinx/cells_map.v | |
| parent | 7fbfcf20d16751f4c1eab0c33848c5c05b970992 (diff) | |
| download | yosys-2e7992efffa1d75cf69c8942d03b53e1b6ec2895.tar.gz yosys-2e7992efffa1d75cf69c8942d03b53e1b6ec2895.tar.bz2 yosys-2e7992efffa1d75cf69c8942d03b53e1b6ec2895.zip | |
Revert "Fix techmapping muxes some more"
This reverts commit 0aae3b4f4361db6d2c6b9c8d69df041f40519cec.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f4b7888b0..85f174d3d 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -225,7 +225,7 @@ module \$__XILINX_SHIFTX (A, B, Y); else if (A_WIDTH <= 2 ** 4) begin localparam a_width0 = 2 ** 2; localparam num_mux8 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH % a_width0; + localparam a_widthN = A_WIDTH - num_mux8*a_width0; wire [a_width0-1:0] T; for (i = 0; i < a_width0; i++) if (i < num_mux8) @@ -243,9 +243,9 @@ module \$__XILINX_SHIFTX (A, B, Y); else begin localparam a_width0 = 2 ** 4; localparam num_mux16 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH % a_width0; - wire [(2**(B_WIDTH-4))-1:0] T; - for (i = 0; i < 2 ** (B_WIDTH-4); i++) + localparam a_widthN = A_WIDTH - num_mux16*a_width0; + wire [a_width0-1:0] T; + for (i = 0; i < a_width0; i++) if (i < num_mux16) \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin |