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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 14:43:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 14:43:08 -0700 |
| commit | a8c49168fb1e5e665e126c65dc454183a6d7826b (patch) | |
| tree | 7cda5e7a9046a7fd024888912e62d0b7d9a7be75 /techlibs/xilinx/cells_map.v | |
| parent | 7166dbe418420bf8f0696b21bff22d5f66a4cc8e (diff) | |
| download | yosys-a8c49168fb1e5e665e126c65dc454183a6d7826b.tar.gz yosys-a8c49168fb1e5e665e126c65dc454183a6d7826b.tar.bz2 yosys-a8c49168fb1e5e665e126c65dc454183a6d7826b.zip | |
Run muxpack and muxcover in synth_xilinx
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4acf04744..8537dc479 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -250,3 +250,15 @@ module \$__XILINX_MUX_ (A, B, Y); end endgenerate endmodule + +module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); +input A, B, C, D, E, F, G, H, S, T, U; +output Y; + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y)); +endmodule + +module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); +input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; +output Y; + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y)); +endmodule |