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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 12:35:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 12:35:41 -0700 |
| commit | b1a048a703b12bc02433d8c2c98b4b35cc799979 (patch) | |
| tree | fb5a70d2a7ddd47599561a2f615d85db4e3a93da /techlibs/xilinx/cells_map.v | |
| parent | bee5d2b21a721b5b2d28cc9326b3d51573167038 (diff) | |
| download | yosys-b1a048a703b12bc02433d8c2c98b4b35cc799979.tar.gz yosys-b1a048a703b12bc02433d8c2c98b4b35cc799979.tar.bz2 yosys-b1a048a703b12bc02433d8c2c98b4b35cc799979.zip | |
Extend using A[1] to preserve don't care
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index e81ff8f53..f20fe253e 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -203,7 +203,15 @@ module \$__XILINX_SHIFTX (A, B, Y); MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y)); end else if (A_WIDTH <= 4) begin - wire [4-1:0] Ax = {{{4-A_WIDTH}{1'bx}}, A}; + wire [4-1:0] Ax; + if (A_WIDTH == 4) + assign Ax = A; + else + // Rather than extend with 1'bx which gets flattened to 1'b0 + // causing the "don't care" status to get lost, extend with + // the same driver of F7B.I0 so that we can optimise F7B away + // later + assign Ax = {A[1], A}; \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y)); end else if (A_WIDTH <= 8) begin |