diff options
| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-04 09:44:00 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-04 09:44:00 +0100 |
| commit | fcce94010f3282e7f7d3f602b3e710cb7ce524ee (patch) | |
| tree | 7be607ebe174deb68e5c78a765ffff647cd4af99 /techlibs/xilinx/cells_map.v | |
| parent | 2abe38e73e51204976129c776447c2d40578c32f (diff) | |
| download | yosys-fcce94010f3282e7f7d3f602b3e710cb7ce524ee.tar.gz yosys-fcce94010f3282e7f7d3f602b3e710cb7ce524ee.tar.bz2 yosys-fcce94010f3282e7f7d3f602b3e710cb7ce524ee.zip | |
xilinx: Add tristate buffer mapping. (#1528)
Fixes #1225.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index a15884ec4..de2068bc5 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -363,3 +363,11 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); else MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule + +module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO); + IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO)); +endmodule + +module \$__XILINX_TOUTPAD (input I, OE, output O); + OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE)); +endmodule |