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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-18 18:15:03 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-19 01:42:40 +0200 |
| commit | aee439360bba642dcbffe5b803aa9a994b11d183 (patch) | |
| tree | a5c15b4a6172ea3ff651f88174fff7d5269ad1c2 /techlibs/xilinx/cells_map.v | |
| parent | 2d573a0ff680eb9f38358943fbf134f765ba1451 (diff) | |
| download | yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.gz yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.bz2 yosys-aee439360bba642dcbffe5b803aa9a994b11d183.zip | |
Add force_downto and force_upto wire attributes.
Fixes #2058.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index cc180f2b9..801949d22 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -184,8 +184,11 @@ module \$__XILINX_SHIFTX (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; @@ -321,8 +324,11 @@ module _90__XILINX_SHIFTX (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); |