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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 22:56:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 22:56:19 -0700 |
| commit | de404535538fe4d2548be82724515961e6e92519 (patch) | |
| tree | cc91f7de77ba146e0e1a568791b2a9c20cc97dee /techlibs/xilinx/cells_map.v | |
| parent | 7f964859ec99500e471853f5914b6e5b7c35a031 (diff) | |
| download | yosys-de404535538fe4d2548be82724515961e6e92519.tar.gz yosys-de404535538fe4d2548be82724515961e6e92519.tar.bz2 yosys-de404535538fe4d2548be82724515961e6e92519.zip | |
Reword
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index d48a3f15c..63095880e 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -202,7 +202,7 @@ module \$__XILINX_SHIFTX (A, B, Y); end else if (A_WIDTH <= 2 ** 3) begin // Rather than extend with 1'bx which gets flattened to 1'b0 - // causing the "don't care" state to get lost, extend with MSB + // causing the "don't care" status to get lost, extend with MSB // so that we can recognise again later when mapping MUXF78 wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A}; wire T0 = B[0] ? Ax[1] : Ax[0]; @@ -213,7 +213,7 @@ module \$__XILINX_SHIFTX (A, B, Y); end else if (A_WIDTH <= 2 ** 4) begin // Rather than extend with 1'bx which gets flattened to 1'b0 - // causing the "don't care" state to get lost, extend with MSB + // causing the "don't care" status to get lost, extend with MSB // so that we can recognise again later when mapping MUXF78 wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A}; wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2] |