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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 23:05:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 23:05:48 -0700 |
| commit | d4ab43d9403899dcae74a24e71385fd959de98f8 (patch) | |
| tree | c4ef25c88487821124b0e097d894db8ce1fb9bbf /techlibs/xilinx/cells_map.v | |
| parent | 939a225f921efc4276121fe957f545a98d252fa0 (diff) | |
| download | yosys-d4ab43d9403899dcae74a24e71385fd959de98f8.tar.gz yosys-d4ab43d9403899dcae74a24e71385fd959de98f8.tar.bz2 yosys-d4ab43d9403899dcae74a24e71385fd959de98f8.zip | |
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Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 7c67c7a79..39427cc90 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -197,6 +197,9 @@ module \$__XILINX_SHIFTX (A, B, Y); MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y)); end else if (A_WIDTH <= 4) begin + // Rather than extend with 1'bx which gets flattened to 1'b0 + // causing the "don't care" status to get lost, extend with MSB + // so that we can recognise again later when mapping MUXF78 wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A}; \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y)); end |