iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	Eddie Hung	2020-05-14	1	-171/+0
*	xilinx: consider DSP48E1.ADREG	Eddie Hung	2020-03-04	1	-2/+3
*	xilinx: cleanup DSP48E1 handling for abc9	Eddie Hung	2020-03-04	1	-50/+104
*	xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v	Eddie Hung	2020-03-04	1	-1/+7
*	abc9_ops: use TimingInfo for -prep_{lut,box} too	Eddie Hung	2020-02-27	1	-7/+10
*	Update xilinx for ABC9	Eddie Hung	2020-02-27	1	-11/+0
*	xilinx: improve specify functionality	Eddie Hung	2020-02-27	1	-2/+4
*	Auto-generate .box/.lut files from specify blocks	Eddie Hung	2020-02-27	1	-10/+80
*	Merge branch 'eddie/abc9_refactor' into eddie/abc9_required	Eddie Hung	2020-01-27	1	-1/+1
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\| *	Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0	Eddie Hung	2020-01-22	1	-1/+1
* \|	Add abc9_ops -check, -prep_times, -write_box for required times	Eddie Hung	2020-01-10	1	-0/+5
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*	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2020-01-06	1	-140/+15
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\| *	Rework abc9's DSP48E1 model	Eddie Hung	2020-01-01	1	-140/+15
* \|	Fix attributes on $__ABC9_ASYNC[01] whitebox	Eddie Hung	2019-12-31	1	-2/+2
* \|	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	Eddie Hung	2019-12-19	1	-3/+11
* \|	Add blackbox model for $__ABC9_FF_ so that clock partitioning works	Eddie Hung	2019-11-20	1	-0/+3
* \|	Do not require changes to cells_sim.v; try and work out comb model	Eddie Hung	2019-10-05	1	-4/+1
* \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	1	-0/+7
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*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-0/+190