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* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-0/+1
* synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-061-7/+1
* xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-231-0/+2
* xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-231-1/+3
* xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-221-1/+7
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-6/+6
* Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-231-1/+0
* Add a xilinx_finalise passEddie Hung2019-09-231-0/+1
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-1/+4
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| * xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-1/+4
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-111-1/+2
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| * synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-071-1/+2
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-0/+3
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-2/+2
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| * | Use abc_{map,unmap,model}.vEddie Hung2019-08-201-1/+3
| * | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-161-3/+12
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-101-0/+1
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-011-0/+2
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| * | | | | Wrap FDRE with $__ABC_FDRE containing combEddie Hung2019-06-151-0/+1
* | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-201-2/+2
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| * | | | | Update Makefile tooEddie Hung2019-07-181-2/+2
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* / | | | Oops forgot these filesEddie Hung2019-07-151-0/+1
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* | | / synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-111-3/+12
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-291-0/+2
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| * | install *_nowide.lut filesEddie Hung2019-06-291-0/+2
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* / Revert "Remove wide mux inference"Eddie Hung2019-06-141-0/+1
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* Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-141-2/+2
* Remove wide mux inferenceEddie Hung2019-06-121-1/+0
* Add mux_map.v for wide muxEddie Hung2019-06-041-0/+1
* Cleanup, call pmux2shiftx even without -nosrlEddie Hung2019-04-221-3/+2
* Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-161-0/+1
* Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-091-0/+1
* Add techlibs/xilinx/cells.boxEddie Hung2019-04-091-0/+1
* Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-1/+2
* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-071-1/+0
* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-101-0/+1
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-191-0/+1
* Switched to Python 3Clifford Wolf2015-08-221-1/+1
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-161-1/+1
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-161-1/+7
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-6/+2
* Verific build fixesClifford Wolf2015-05-171-2/+2
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-091-0/+3
* Added support for initialized xilinx bramsClifford Wolf2015-04-061-0/+21
* Added Xilinx bram black-box modulesClifford Wolf2015-04-061-0/+1
* Various cleanups in xilinx techlibClifford Wolf2015-01-181-3/+3
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-171-0/+1
* Added add_share_file Makefile macroClifford Wolf2015-01-081-13/+4
* Towards Xilinx bram supportClifford Wolf2015-01-041-1/+9