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* greenpak4: Changed port names on GP_SPI for clarityAndrew Zonenberg2016-12-201-4/+4
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* greenpak4: Initial implementation of GP_SPI cellAndrew Zonenberg2016-12-201-0/+27
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* greenpak4: Updated GP_DCMP cell modelAndrew Zonenberg2016-12-171-2/+20
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* greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.Andrew Zonenberg2016-12-161-5/+10
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* greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed ↵Andrew Zonenberg2016-12-151-5/+24
| | | | interface to GP_DCMPMUX
* greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
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* greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
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* greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
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* greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
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* greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
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* greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
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* Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
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* greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
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* greenpak4: Can now techmap inferred D latches (without set/reset or output ↵Andrew Zonenberg2016-12-103-0/+17
| | | | inverter)
* greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵Andrew Zonenberg2016-12-101-15/+15
| | | | name for consistency
* Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
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* Initial implementation of techlib support for GreenPAK latches. ↵Andrew Zonenberg2016-12-052-0/+120
| | | | Instantiation only, no behavioral inference yet.
* Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
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* Fixed typo in last commitAndrew Zonenberg2016-10-181-1/+1
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* greenpak4: Added GP_PGEN cell definitionAndrew Zonenberg2016-10-181-0/+21
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* Added GLITCH_FILTER parameter to GP_DELAYAndrew Zonenberg2016-10-181-3/+2
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* greenpak4: added model for GP_EDGEDET blockAndrew Zonenberg2016-10-181-0/+10
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* greenpak4: Changed parameters for GP_SYSRESETAndrew Zonenberg2016-10-161-1/+2
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* Added greenpak4_dffinvClifford Wolf2016-08-153-0/+199
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* greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-142-19/+19
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* greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-142-0/+68
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* greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
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* synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
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* Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
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* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
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* Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
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* greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
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* Added "nlutmap -assert"Clifford Wolf2016-06-091-3/+3
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* Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
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* Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
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* Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
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* Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
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* Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
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* Changed order of passes for better handling of INIT attributes on "output ↵Andrew Zonenberg2016-05-041-2/+2
| | | | reg" FFs
* Renamed module parameterAndrew Zonenberg2016-05-041-4/+4
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* Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT ↵Andrew Zonenberg2016-05-043-18/+1
| | | | cells instead of extract
* Fixed incorrect signal naming in GP_IOBUFAndrew Zonenberg2016-05-041-2/+2
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* Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-035-2/+29
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* Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
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* Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
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* Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
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* Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
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* Removed VIN_BUF_ENAndrew Zonenberg2016-04-241-1/+0
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* Renamed VOUT to OUT on GP_ACMP cellAndrew Zonenberg2016-04-231-1/+3
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* Added GP_ACMP cellAndrew Zonenberg2016-04-231-0/+12
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