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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-11 10:04:00 +0800 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-11 10:04:00 +0800 |
| commit | c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40 (patch) | |
| tree | 3f23399c1213d4f49133fd8b6e5677709625ffcf /techlibs/greenpak4 | |
| parent | 8f3d1f8fcfb5f853b1dfddc1073b4e79a81d6bd8 (diff) | |
| download | yosys-c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40.tar.gz yosys-c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40.tar.bz2 yosys-c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40.zip | |
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index ca3e6cdbf..1b899e8e8 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -18,7 +18,11 @@ endmodule module GP_ABUF(input wire IN, output wire OUT); assign OUT = IN; - + + //must be 1, 5, 20, 50 + //values >1 only available with Vdd > 2.7V + parameter BANDWIDTH_KHZ = 1; + //cannot simulate mixed signal IP endmodule @@ -412,6 +416,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); endmodule +module GP_PWRDET(output reg VDD_LOW); + initial VDD_LOW = 0; +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; |