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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-02 20:29:39 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-02 20:29:39 -0700 |
| commit | 9fc9d5f1fb1eea47118c00ecad1352ec84fd3047 (patch) | |
| tree | eab8c1c0126169bd47912390523ef7d82c739b90 /techlibs/greenpak4 | |
| parent | 79460208c928e62c608d71c0d6d484293835e8dc (diff) | |
| download | yosys-9fc9d5f1fb1eea47118c00ecad1352ec84fd3047.tar.gz yosys-9fc9d5f1fb1eea47118c00ecad1352ec84fd3047.tar.bz2 yosys-9fc9d5f1fb1eea47118c00ecad1352ec84fd3047.zip | |
Added comment to clarify GP_ABUF cell
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 04bce8771..7555a7ac8 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -17,6 +17,8 @@ module GP_ABUF(input wire IN, output wire OUT); assign OUT = IN; + //cannot simulate mixed signal IP + endmodule module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT); |