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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:19:08 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:19:08 +0800 |
| commit | 3690aa556c5f1e51634fe2fc51cbffd174e76480 (patch) | |
| tree | 0e811d3065e3c855c4228a015ce4cb6994088b71 /techlibs/greenpak4 | |
| parent | 3491d338634b76639d46770c04f907ac60f19a96 (diff) | |
| download | yosys-3690aa556c5f1e51634fe2fc51cbffd174e76480.tar.gz yosys-3690aa556c5f1e51634fe2fc51cbffd174e76480.tar.bz2 yosys-3690aa556c5f1e51634fe2fc51cbffd174e76480.zip | |
greenpak4: More fixups of GP_DCMPx cells
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 25a49ac06..cd5086951 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -132,18 +132,12 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); endmodule -module GP_DCMPREF(output OUT); +module GP_DCMPREF(output reg[7:0]OUT); parameter[7:0] REF_VAL = 8'h00; - wire[7:0] OUT = REF_VAL; + initial OUT = REF_VAL; endmodule -module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT); - wire[1:0] SEL; - wire[7:0] IN0; - wire[7:0] IN1; - wire[7:0] IN2; - wire[7:0] IN3; - reg[7:0] OUT; +module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUT); always @(*) begin case(SEL) |