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authorAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-23 22:33:36 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2016-04-23 22:33:36 -0700
commit512486dcf37f779e6271e299eb186ab2559eb344 (patch)
tree15abb43ba40d6836947c7b4f58a6c74143ab8522 /techlibs/greenpak4
parent096c25d29d7e66003123dc4700ae72b0a4c10ca2 (diff)
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Added GP_ACMP cell
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r--techlibs/greenpak4/cells_sim.v12
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 706e955b6..e6b5db750 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -13,6 +13,18 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
+module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOUT = 0);
+
+ parameter BANDWIDTH = "HIGH";
+ parameter VIN_BUF_EN = 0;
+ parameter VIN_ATTEN = 1;
+ parameter VIN_ISRC_EN = 0;
+ parameter HYSTERESIS = 0;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
module GP_BANDGAP(output reg OK, output reg VOUT);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;