diff options
| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-08-13 22:27:58 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-08-13 22:27:58 -0700 |
| commit | 2b062c48cb4405f4a1bb6bd49edaf687bbc2cc4e (patch) | |
| tree | 8010dfccb80f6ef44509561edf63c250615e84f6 /techlibs/greenpak4 | |
| parent | 6ac67eac10cfd3e9508ef02f6301455fc3c13451 (diff) | |
| download | yosys-2b062c48cb4405f4a1bb6bd49edaf687bbc2cc4e.tar.gz yosys-2b062c48cb4405f4a1bb6bd49edaf687bbc2cc4e.tar.bz2 yosys-2b062c48cb4405f4a1bb6bd49edaf687bbc2cc4e.zip | |
greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index ca8556a85..ceec28696 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -275,15 +275,15 @@ module GP_POR(output reg RST_DONE); endmodule -module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); +module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC); parameter PWRDN_EN = 0; parameter AUTO_PWRDN = 0; - parameter PRE_DIV = 1; + parameter HARDIP_DIV = 1; parameter FABRIC_DIV = 1; parameter OSC_FREQ = "25k"; - initial CLKOUT_PREDIV = 0; + initial CLKOUT_HARDIP = 0; initial CLKOUT_FABRIC = 0; //output dividers not implemented for simulation @@ -291,7 +291,7 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC) always begin if(PWRDN) begin - CLKOUT_PREDIV = 0; + CLKOUT_HARDIP = 0; CLKOUT_FABRIC = 0; end else begin @@ -306,21 +306,21 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC) #250; end - CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_HARDIP = ~CLKOUT_HARDIP; CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end endmodule -module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); +module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC); parameter PWRDN_EN = 0; parameter AUTO_PWRDN = 0; - parameter PRE_DIV = 1; + parameter HARDIP_DIV = 1; parameter FABRIC_DIV = 1; - initial CLKOUT_PREDIV = 0; + initial CLKOUT_HARDIP = 0; initial CLKOUT_FABRIC = 0; //output dividers not implemented for simulation @@ -328,13 +328,13 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI always begin if(PWRDN) begin - CLKOUT_PREDIV = 0; + CLKOUT_HARDIP = 0; CLKOUT_FABRIC = 0; end else begin //half period of 27 MHz #18.518; - CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_HARDIP = ~CLKOUT_HARDIP; CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end |