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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:18 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:18 -0700 |
| commit | b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f (patch) | |
| tree | f5779aa2a5ed58bb1eb744220f34685f91d0dd16 /techlibs/greenpak4 | |
| parent | 85ee88b0ee13eb49bb255d7e66a62fce823c028a (diff) | |
| download | yosys-b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f.tar.gz yosys-b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f.tar.bz2 yosys-b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f.zip | |
Fixed extra semicolon
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index c4e5a9de1..5a59a06b4 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ps; +`timescale 1ns/1ps module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; |