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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 19:33:26 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 19:33:26 -0700 |
| commit | a818472f0c1a5baa8fb6ba6f4b9a4340058e3616 (patch) | |
| tree | 9ea9162af79cf47ab4dce79436c6cfa99f1471b6 /techlibs/greenpak4 | |
| parent | 2effa497a3328c75e88f4f70e9889428d2ee5524 (diff) | |
| download | yosys-a818472f0c1a5baa8fb6ba6f4b9a4340058e3616.tar.gz yosys-a818472f0c1a5baa8fb6ba6f4b9a4340058e3616.tar.bz2 yosys-a818472f0c1a5baa8fb6ba6f4b9a4340058e3616.zip | |
greenpak4: added model for GP_EDGEDET block
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 8515b985a..8a1794fc1 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -241,6 +241,16 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ); end endmodule +module GP_EDGEDET(input IN, output reg OUT); + + parameter EDGE_DIRECTION = "RISING"; + parameter DELAY_STEPS = 1; + parameter GLITCH_FILTER = 0; + + //not implemented for simulation + +endmodule + module GP_IBUF(input IN, output OUT); assign OUT = IN; endmodule |