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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:42 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:42 -0700 |
| commit | 41bbad4e4c25bc1b0227348ec0329187c8688c4b (patch) | |
| tree | 5ee87a728654ee50db2915c3374be2bd767ff7b4 /techlibs/greenpak4 | |
| parent | b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f (diff) | |
| download | yosys-41bbad4e4c25bc1b0227348ec0329187c8688c4b.tar.gz yosys-41bbad4e4c25bc1b0227348ec0329187c8688c4b.tar.bz2 yosys-41bbad4e4c25bc1b0227348ec0329187c8688c4b.zip | |
Fixed typo in port name
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 5a59a06b4..b9cfbe665 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge nRST) begin + always @(posedge CLK, negedge nRST) begin if(!nRST) shreg = 0; |