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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 20:42:44 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 20:42:44 -0700 |
commit | e78fa157a3decfc6e595089c7d73b9cca785b252 (patch) | |
tree | ecc0c6f80e1b73ac650036e3fae2cc6a1f421417 /techlibs/greenpak4 | |
parent | 091d32b563ecdd9e5a3377811fdd2411dc9fd1bc (diff) | |
download | yosys-e78fa157a3decfc6e595089c7d73b9cca785b252.tar.gz yosys-e78fa157a3decfc6e595089c7d73b9cca785b252.tar.bz2 yosys-e78fa157a3decfc6e595089c7d73b9cca785b252.zip |
greenpak4: Added GP_PGEN cell definition
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 668c69829..76bf058d2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -305,6 +305,27 @@ module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg endmodule +module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); + initial OUT = 0; + parameter PATTERN_DATA = 16'h0; + parameter PATTERN_LEN = 4'd16; + + reg[3:0] count = 0; + always @(posedge CLK) begin + if(!nRST) + OUT <= PATTERN_DATA[0]; + + else begin + count <= count + 1; + OUT <= PATTERN_DATA[count]; + + if( (count + 1) == PATTERN_LEN) + count <= 0; + end + end + +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; |