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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-24 17:01:21 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-24 17:01:21 -0700 |
| commit | 349d7172023e9ee38b8e25e3bd04e2dfd0af1e62 (patch) | |
| tree | b420d06d2a5e2ae407349500d855bdcdd58e9faf /techlibs/greenpak4 | |
| parent | 6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5 (diff) | |
| download | yosys-349d7172023e9ee38b8e25e3bd04e2dfd0af1e62.tar.gz yosys-349d7172023e9ee38b8e25e3bd04e2dfd0af1e62.tar.bz2 yosys-349d7172023e9ee38b8e25e3bd04e2dfd0af1e62.zip | |
Removed VIN_BUF_EN
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 586b7a9b8..1152ffe63 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -16,7 +16,6 @@ endmodule module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT); parameter BANDWIDTH = "HIGH"; - parameter VIN_BUF_EN = 0; parameter VIN_ATTEN = 1; parameter VIN_ISRC_EN = 0; parameter HYSTERESIS = 0; |