iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	gowin: Add oscillator primitives	Tim Pambor	2022-03-28	1	-0/+34
*	gowin: add support for Double Data Rate primitives	YRabbit	2022-03-14	1	-0/+25
*	gowin: Remove unnecessary attributes	YRabbit	2022-02-24	1	-5/+0
*	gowin: Add support for true differential output	YRabbit	2022-02-24	1	-0/+11
*	gowin: Add remaining block RAM blackboxes.	Marcelina Kościelnicka	2022-02-12	1	-72/+527
*	gowin: Fix LUT RAM inference, add more models.	Marcelina Kościelnicka	2022-02-09	1	-39/+238
*	Gowin: deal with active-low tristate (#2971)	Pepijn de Vos	2021-08-20	1	-2/+2
*	synth_gowin: Add rPLL blackbox	Konrad Beckmann	2020-11-11	1	-0/+45
*	synth_gowin: ABC9 support	Dan Ravensloft	2020-07-05	1	-20/+323
*	gowin: Fix INIT values in sim library.	Marcelina Kościelnicka	2020-07-05	1	-8/+8
*	add IOBUF	Pepijn de Vos	2019-10-28	1	-0/+8
*	add tristate buffer and test	Pepijn de Vos	2019-10-28	1	-0/+6
*	add wide luts	Pepijn de Vos	2019-10-28	1	-0/+35
*	ALU sim tweaks	Pepijn de Vos	2019-10-24	1	-11/+11
*	add negedge DFF	Pepijn de Vos	2019-10-21	1	-8/+113
*	use ADDSUB ALU mode to remove inverters	Pepijn de Vos	2019-10-21	1	-4/+74
*	remove duplicate DFFR	Pepijn de Vos	2019-10-16	1	-10/+0
*	Revert "add MUX support"	Pepijn de Vos	2019-09-06	1	-13/+0
*	add more DFF to sim lib	Pepijn de Vos	2019-09-06	1	-0/+105
*	WIP aditional DFF primitives	Pepijn de Vos	2019-09-05	1	-0/+2
*	add MUX support	Pepijn de Vos	2019-09-05	1	-0/+13
*	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	Diego	2019-04-12	1	-0/+134
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	1	-0/+6
*	Indenting fixes in gowin sim cell lib	Clifford Wolf	2016-11-08	1	-20/+28
*	Added initial version of "synth_gowin"	Clifford Wolf	2016-11-01	1	-0/+51