aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/gowin/cells_sim.v
diff options
context:
space:
mode:
authorPepijn de Vos <pepijndevos@gmail.com>2019-10-16 11:24:56 +0200
committerPepijn de Vos <pepijndevos@gmail.com>2019-10-16 11:24:56 +0200
commit72323e11a4ee222c0ce928669d33333c46fb25aa (patch)
tree7777fce683417f076bf874d955b96d5ac964c6ce /techlibs/gowin/cells_sim.v
parent2fb20f184aad4e0286afb6b44712cf5bffb531f4 (diff)
downloadyosys-72323e11a4ee222c0ce928669d33333c46fb25aa.tar.gz
yosys-72323e11a4ee222c0ce928669d33333c46fb25aa.tar.bz2
yosys-72323e11a4ee222c0ce928669d33333c46fb25aa.zip
remove duplicate DFFR
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
-rw-r--r--techlibs/gowin/cells_sim.v10
1 files changed, 0 insertions, 10 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b70d1299c..de0cfa9f3 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -38,16 +38,6 @@ module DFFN (output reg Q, input CLK, D);
Q <= D;
endmodule
-module DFFR (output reg Q, input D, CLK, RESET);
- parameter [0:0] INIT = 1'b0;
- initial Q = INIT;
- always @(posedge CLK) begin
- if (RESET)
- Q <= 1'b0;
- else
- Q <= D;
- end
-endmodule // DFFR (positive clock edge; synchronous reset)
module DFFE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;