diff options
| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:18:01 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:18:01 +0100 |
| commit | 903f9973913371452005eb173ac50fec1d5d1447 (patch) | |
| tree | b160b35c7a1048dc5d1ef2f63a6159f5aef6fe1f /techlibs/gowin/cells_sim.v | |
| parent | 9517525224c7bc4b8ac7d093066485888a337b76 (diff) | |
| download | yosys-903f9973913371452005eb173ac50fec1d5d1447.tar.gz yosys-903f9973913371452005eb173ac50fec1d5d1447.tar.bz2 yosys-903f9973913371452005eb173ac50fec1d5d1447.zip | |
add tristate buffer and test
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 0fe2c8c52..cc1ac48e6 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -302,6 +302,12 @@ module OBUF(output O, input I); assign O = I; endmodule +module TBUF (O, I, OEN); + input I, OEN; + output O; + assign O = OEN ? I : 1'bz; +endmodule + module GSR (input GSRI); wire GSRO = GSRI; endmodule |