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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 19:12:47 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 19:12:47 +0200 |
| commit | 5168b6ffa4047340b3412aa17be7e2d7ac587ee1 (patch) | |
| tree | eeca2763173ea86cac8e2f1ece68b930e22254f3 /techlibs/gowin/cells_sim.v | |
| parent | 47374a495d3cbfa424cbe312aa4762e7c4e855ff (diff) | |
| download | yosys-5168b6ffa4047340b3412aa17be7e2d7ac587ee1.tar.gz yosys-5168b6ffa4047340b3412aa17be7e2d7ac587ee1.tar.bz2 yosys-5168b6ffa4047340b3412aa17be7e2d7ac587ee1.zip | |
WIP aditional DFF primitives
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 98dfef9bf..c8475b28f 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -62,6 +62,8 @@ module DFFR (output reg Q, input D, CLK, RESET); end endmodule // DFFR (positive clock edge; synchronous reset) +// TODO add more DFF sim cells + module VCC(output V); assign V = 1; endmodule |