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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 12:49:08 +0100 |
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committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 12:49:08 +0100 |
commit | f88335a8a5284a8e69230ec20eeeca6c02b055bf (patch) | |
tree | 2eeb2876fd7eb9fcae6216c72ac940fac94bea6c /techlibs/gowin/cells_sim.v | |
parent | 5fad53b504a7ac05fb959f0ca84829bd550aac47 (diff) | |
download | yosys-f88335a8a5284a8e69230ec20eeeca6c02b055bf.tar.gz yosys-f88335a8a5284a8e69230ec20eeeca6c02b055bf.tar.bz2 yosys-f88335a8a5284a8e69230ec20eeeca6c02b055bf.zip |
add wide luts
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
-rw-r--r-- | techlibs/gowin/cells_sim.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 9dac2c2c2..0fe2c8c52 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,6 +24,41 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule +module MUX2 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + assign O = S0 ? I1 : I0; +endmodule + +module MUX2_LUT5 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut5 (O, I0, I1, S0); +endmodule + +module MUX2_LUT6 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut6 (O, I0, I1, S0); +endmodule + +module MUX2_LUT7 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut7 (O, I0, I1, S0); +endmodule + +module MUX2_LUT8 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut8 (O, I0, I1, S0); +endmodule + module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; |