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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:33:05 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:33:05 +0100 |
| commit | 0f6269b04c4a5f44b62021759507bcbe61a7c8d7 (patch) | |
| tree | 17f1fb8a1e4532045c86cbb7151fc15a02481be2 /techlibs/gowin/cells_sim.v | |
| parent | 903f9973913371452005eb173ac50fec1d5d1447 (diff) | |
| download | yosys-0f6269b04c4a5f44b62021759507bcbe61a7c8d7.tar.gz yosys-0f6269b04c4a5f44b62021759507bcbe61a7c8d7.tar.bz2 yosys-0f6269b04c4a5f44b62021759507bcbe61a7c8d7.zip | |
add IOBUF
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index cc1ac48e6..a67855dab 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -308,6 +308,14 @@ module TBUF (O, I, OEN); assign O = OEN ? I : 1'bz; endmodule +module IOBUF (O, IO, I, OEN); + input I,OEN; + output O; + inout IO; + assign IO = OEN ? I : 1'bz; + assign I = IO; +endmodule + module GSR (input GSRI); wire GSRO = GSRI; endmodule |