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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 13:36:41 +0200 |
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committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 13:36:41 +0200 |
commit | 3eff2271d0fe25632f7e6b22cf0be078d2cd9990 (patch) | |
tree | 45ac22fbb2a8564f37ab3c3a48c6809d5a21646f /techlibs/gowin/cells_sim.v | |
parent | ae93c034adc8a7d14a9f39175dacdddda75ea7a2 (diff) | |
download | yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.tar.gz yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.tar.bz2 yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.zip |
add MUX support
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
-rw-r--r-- | techlibs/gowin/cells_sim.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index ebb238bad..98dfef9bf 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,6 +24,19 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule +module MUX2 (I0, I1, S0, O); +input I0, I1, S0; +output O; +assign O = S0 ? I1 : I0; +endmodule + +module MUX4 (I0, I1, I2, I3, S0, S1, O); +input I0, I1, I2, I3, S0, S1; +output O; +assign O = S1 ? (S0 ? I3 : I2) : + (S0 ? I1 : I0); +endmodule + module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; |