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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 03:03:48 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 03:03:48 +0200 |
| commit | 9beed4d771359f1757682cedf5a1175db3408959 (patch) | |
| tree | 27f92eb2f7282fdaf628201bfea7abd630176bb4 /techlibs/gowin/cells_sim.v | |
| parent | c6765443fdb57938418fb2b80bf56cda0e7d229b (diff) | |
| download | yosys-9beed4d771359f1757682cedf5a1175db3408959.tar.gz yosys-9beed4d771359f1757682cedf5a1175db3408959.tar.bz2 yosys-9beed4d771359f1757682cedf5a1175db3408959.zip | |
gowin: Fix INIT values in sim library.
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index a67855dab..da5175975 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -77,7 +77,7 @@ endmodule // DFFE (positive clock edge; clock enable) module DFFS (output reg Q, input D, CLK, SET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(posedge CLK) begin if (SET) @@ -89,7 +89,7 @@ endmodule // DFFS (positive clock edge; synchronous set) module DFFSE (output reg Q, input D, CLK, CE, SET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(posedge CLK) begin if (SET) @@ -125,7 +125,7 @@ endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over module DFFP (output reg Q, input D, CLK, PRESET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(posedge CLK or posedge PRESET) begin if(PRESET) @@ -137,7 +137,7 @@ endmodule // DFFP (positive clock edge; asynchronous preset) module DFFPE (output reg Q, input D, CLK, CE, PRESET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(posedge CLK or posedge PRESET) begin if(PRESET) @@ -190,7 +190,7 @@ endmodule // DFFNE (negative clock edge; clock enable) module DFFNS (output reg Q, input D, CLK, SET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(negedge CLK) begin if (SET) @@ -202,7 +202,7 @@ endmodule // DFFNS (negative clock edge; synchronous set) module DFFNSE (output reg Q, input D, CLK, CE, SET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(negedge CLK) begin if (SET) @@ -238,7 +238,7 @@ endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence ove module DFFNP (output reg Q, input D, CLK, PRESET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(negedge CLK or posedge PRESET) begin if(PRESET) @@ -250,7 +250,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset) module DFFNPE (output reg Q, input D, CLK, CE, PRESET); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; initial Q = INIT; always @(negedge CLK or posedge PRESET) begin if(PRESET) |