diff options
| author | Diego H <dhdezr@gmail.com> | 2018-12-03 20:08:35 -0600 |
|---|---|---|
| committer | Diego H <dhdezr@gmail.com> | 2018-12-03 20:08:35 -0600 |
| commit | 819ca7309620b3791c7b93de44990ffb4fceb30f (patch) | |
| tree | 08fd9f5adfd9a8afb3f58600e67907c7346b0cee /techlibs/gowin/cells_sim.v | |
| parent | 47c89d600c11aee97e325351d295781169d62978 (diff) | |
| download | yosys-819ca7309620b3791c7b93de44990ffb4fceb30f.tar.gz yosys-819ca7309620b3791c7b93de44990ffb4fceb30f.tar.bz2 yosys-819ca7309620b3791c7b93de44990ffb4fceb30f.zip | |
Changes in GoWin synth commands and ALU primitive support
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 947942626..14441c2fc 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -57,3 +57,9 @@ endmodule module GSR (input GSRI); wire GSRO = GSRI; endmodule + +module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM); + parameter [3:0] ALU_MODE = 0; // default 0 = ADD + assign {COUT, SUM} = CIN + I1 + I0; +endmodule // alu + |