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authorPepijn de Vos <pepijndevos@gmail.com>2019-09-06 11:28:17 +0200
committerPepijn de Vos <pepijndevos@gmail.com>2019-09-06 11:28:17 +0200
commit2fb20f184aad4e0286afb6b44712cf5bffb531f4 (patch)
tree65dcce4f423065bc8193ae15bdd7c980cc8ecc6d /techlibs/gowin/cells_sim.v
parent96efa63f16ae30927759b374c86a68753199d0d2 (diff)
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Revert "add MUX support"
It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
-rw-r--r--techlibs/gowin/cells_sim.v13
1 files changed, 0 insertions, 13 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index a2f60b99e..b70d1299c 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -24,19 +24,6 @@ module LUT4(output F, input I0, I1, I2, I3);
assign F = I0 ? s1[1] : s1[0];
endmodule
-module MUX2 (I0, I1, S0, O);
-input I0, I1, S0;
-output O;
-assign O = S0 ? I1 : I0;
-endmodule
-
-module MUX4 (I0, I1, I2, I3, S0, S1, O);
-input I0, I1, I2, I3, S0, S1;
-output O;
-assign O = S1 ? (S0 ? I3 : I2) :
- (S0 ? I1 : I0);
-endmodule
-
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;