iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Missing (* mul2dsp *) for sliceB	Eddie Hung	2019-09-27	1	-2/+2
*	Stop trying to be too smart by prematurely optimising	Eddie Hung	2019-09-26	1	-34/+6
*	mul2dsp.v slice names	Eddie Hung	2019-09-25	1	-5/+5
*	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	Eddie Hung	2019-09-25	1	-3/+1
*	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"	Eddie Hung	2019-09-25	1	-2/+6
*	Revert "No need for $__mul anymore?"	Eddie Hung	2019-09-25	1	-8/+8
*	Remove _TECHMAP_CELLTYPE_ check since all $mul	Eddie Hung	2019-09-25	1	-6/+2
*	No need for $__mul anymore?	Eddie Hung	2019-09-25	1	-8/+8
*	Fix signedness bug	Eddie Hung	2019-09-20	1	-2/+2
*	Be sensitive to signedness	Eddie Hung	2019-09-10	1	-20/+21
*	Really get rid of 'opt_expr -fine' by being explicit	Eddie Hung	2019-09-10	1	-6/+33
*	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-05	2	-0/+2
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\| *	Use a dummy box file if none specified	Eddie Hung	2019-08-28	2	-0/+2
* \|	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	Eddie Hung	2019-08-30	1	-1/+1
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\| * \|	Merge branch 'master' into xc7dsp	David Shah	2019-08-30	1	-1/+1
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\| \| *	Missing newline	Eddie Hung	2019-08-20	1	-1/+1
* \| \|	Only swap ports if $mul and not $__mul	Eddie Hung	2019-08-13	1	-1/+1
* \| \|	Add DSP_A_MAXWIDTH_PARTIAL, refactor	Eddie Hung	2019-08-13	1	-144/+110
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* \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-12	1	-8/+36
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\| *	Reformat so it shows up/looks nice when "help $alu" and "help $alu+"	Eddie Hung	2019-08-09	1	-25/+34
\| *	A bit more on where $lcu comes from	Eddie Hung	2019-08-09	1	-0/+2
\| *	Add more comments	Eddie Hung	2019-08-09	1	-4/+18
\| *	Add a few comments to document $alu and $lcu	Eddie Hung	2019-08-08	1	-9/+12
* \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-07	1	-0/+19
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\| *	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	Clifford Wolf	2019-08-06	1	-0/+19
* \|	Trim Y_WIDTH	Eddie Hung	2019-08-01	1	-5/+3
* \|	Add DSP_SIGNEDONLY back	Eddie Hung	2019-08-01	1	-0/+16
* \|	DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH	Eddie Hung	2019-08-01	1	-4/+11
* \|	Revert "Do not do sign extension in techmap; let packer do it"	Eddie Hung	2019-08-01	1	-5/+14
* \|	Fix B_WIDTH > DSP_B_MAXWIDTH case	Eddie Hung	2019-08-01	1	-32/+14
* \|	Do not compute sign bit if result is zero	Eddie Hung	2019-07-31	1	-1/+2
* \|	For signed multipliers, compute sign bit separately...	Eddie Hung	2019-07-31	1	-23/+42
* \|	Fix spacing	Eddie Hung	2019-07-26	1	-3/+3
* \|	Add copyright header, comment on cascade	Eddie Hung	2019-07-24	1	-4/+34
* \|	Typo for Y_WIDTH	Eddie Hung	2019-07-23	1	-1/+1
* \|	Use minimum sized width wires	Eddie Hung	2019-07-22	1	-7/+13
* \|	Indirection via $__soft_mul	Eddie Hung	2019-07-19	1	-9/+9
* \|	Do not do sign extension in techmap; let packer do it	Eddie Hung	2019-07-19	1	-14/+5
* \|	Do not $mul -> $__mul if A and B are less than maxwidth	Eddie Hung	2019-07-19	1	-1/+3
* \|	Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too	Eddie Hung	2019-07-19	1	-28/+68
* \|	Merge branch 'xc7dsp' into ice40dsp	Eddie Hung	2019-07-19	1	-1/+1
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\| * \|	Fix typo in B	Eddie Hung	2019-07-19	1	-1/+1
\| * \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-07-18	1	-1/+1
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* \| \|	Use sign_headroom instead	Eddie Hung	2019-07-19	1	-4/+4
* \| \|	Do not define `DSP_SIGNEDONLY macro if no exists	Eddie Hung	2019-07-18	1	-4/+3
* \| \|	Merge remote-tracking branch 'origin/master' into ice40dsp	Eddie Hung	2019-07-18	1	-1/+1
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\| * \|	gen_lut to return correctly sized LUT mask	Eddie Hung	2019-07-16	1	-1/+1
\| * \|	Revert "Add "synth -keepdc" option"	Eddie Hung	2019-07-09	1	-13/+2
\| * \|	Add synth -keepdc option	Eddie Hung	2019-07-08	1	-2/+13
* \| \|	mul2dsp to create cells that can be interchanged with $mul	Eddie Hung	2019-07-18	1	-1/+7
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